1. Field of the Invention
The present invention relates to a semiconductor device and a method of controlling the same, and more particularly to a semiconductor device that operates in synchronization with a clock signal and a method of controlling the same. The present invention also relates to an information processing system that uses such a semiconductor device.
2. Description of Related Art
Synchronous dynamic random access memories (DRAMs) that are widely used as a main memory of a computer operate in synchronization with a clock signal. An external controller supplies external command signals synchronous with an external clock signal to a synchronous DRAM. Inside a DRAM, internal commands are decoded and latched in synchronization with an internal clock signal (see Japanese Patent Application Laid-Open Nos. 2003-59263 and 2003-317477.
Since external command signals from an external controller are supplied to a DRAM in synchronization with an external clock signal, predetermined setup margins and hold margins are needed for all active edges (for example, rising edges) of the external command signals. When using an external clock signal having a high frequency, there has thus been a problem of insufficient setup margins and hold margins for external command signals.
One of the possible methods for increasing the setup margin and hold margin of an external command signal is to divide the frequency of an external clock signal inside a DRAM to generate a frequency-divided clock signal having a frequency lower than that of the external clock signal, and perform a latch operation on the external command signal in synchronization with the frequency-divided clock signal. According to such a method, setup margins and hold margins need not be provided for all active edges of the external command signal, but have only to be provided for every n active edges (n is a power of 2) of the external command signal. This allows greater setup margins and hold margins for the external command signal. As employed herein, such an operation, or an operation mode of enabling the input of an external command signal at every n active edges of the external command signal, will be referred to as a “gear down mode.”
Suppose that the gear down mode can be switched ON and OFF. If the frequency of the external clock signal is simply divided when the gear down mode is ON, a large difference occurs between the latch timing when the gear down mode is ON and the latch timing when the gear down mode is OFF. The reason is that when the gear down mode is ON, the external clock signal is passed through the frequency division circuit and the generated frequency-divided clock signal undergoes a predetermined delay. When the gear down mode is OFF, the frequency-division circuit is bypassed and thus causes no delay.
To eliminate such a difference in timing, the internal clock signal needs to be accurately delayed by using delay elements so that the same amount of delay occurs when the gear down mode is OFF as when the gear down mode is ON. The accurate cancellation of a difference in timing needs complicated design with increased design burdens. An element area needed for forming the delay elements also causes a problem of greater chip area.